This invention relates to flash electrically-erasable, programmable read-only memories (Flash EPROMs) and to a method for making such integrated-circuit devices. In particular, this invention relates to a structure and a method for forming an array of EPROM cells.
One conventional structure for memory arrays of the type used herein is described, for example, in U.S. Pat. No. 5,019,527. In prior-art Flash EPROMs of the type described in exemplary U.S. Pat. No. 5,019,527, a horizontal source line connects to the sources of each memory cell in a row of an array of such memory cells. The term "array", as used herein, includes a subarray of several such subarrays on a chip. To flash erase of all of the memory cells in an array, a positive voltage is applied to the common source electrode for that array. With separate common source electrodes for subarrays, each of the subarrays may be erased separately from other subarrays on the chip.
The buried horizontal source lines of the foregoing prior-art arrays are formed by etching through vertical field oxide insulators. The horizontal source lines are formed in alternate spaces between the wordline/floating-gate stacks, with the stacks serving as masking for the self-aligned etching step.
The buried horizontal source lines are connected together by metal vertical source lines, so that all of the sources of the memory cells in an array are connected to a common electrode. Each metal vertical source line typically requires a space equivalent to about one and one-half columns of memory cells. The vertical source lines are placed at suitable intervals of columns of cells to compensate for the relatively high resistance of the buried horizontal source lines.
There is a need for a cost-effective, easy-to-integrate Flash EPROM structure that retains the advantages of the first prior-art structure described above, yet eliminates the need for space-consuming vertical source lines. In addition, there is a need for a Flash EPROM structure that decreases the number of steps for manufacturing the type of memory array described above.